The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductors where each generation has smaller and more complex circuits than the previous generation. In the course of semiconductor evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally produces a relatively high rate of power loss, thus there has been a desire to use a high dielectric constant (high-k) gate dielectrics and metal gate electrodes to improve device performance as feature sizes continue to decrease. In some arrangements of metal integration, patterns etched into a dielectric are filled with metal layers by blanket deposition onto the wafer surface, for example by chemical vapor deposition (CVD).
Chemical mechanical polishing (CMP) has become a key technology driver to achieve local or global wafer planarization for submicron advanced semiconductors. The CMP process is used to planarize and remove excess metal, for example cobalt (Co), over the dielectric and to produce a planar semiconductor structure wherein metal lines or plugs, barrier metal, and exposed dielectric surfaces are coplanar. However, in instances where the semiconductor structure includes a step height between a trench silicide (TS) area and a non-TS area, and where Co is deposited as the metal layer, traditional CMP results in a Co residue remaining on the lower height non-TS area which in turn causes a zero yield in the non-TS area.